Physical Design Engineer - Full Chip Implementation

Summary

Full-time role at Etched, ASIC team. RoleRadar classifies it as solutions & customer. Listed location: San Jose. The posting asks for 10+ years of experience. Skills mentioned include Python, LLMs and Verilog / RTL.

Generated by RoleRadar from facts in the posting. We don't reproduce the job description; read it in full on Etched's job page.

Key facts

Salary

$150K–$375K/yr

Published in the employer's job board data.

Location

• San Jose

Workplace

On-site

From the workplace field on the employer's job board.

Countries

United States

Inferred by RoleRadar from the listed locations.

Experience

10+ years asked for

PhD

Not mentioned

Visa sponsorship

Not stated in the posting

Team

ASIC

Skills mentioned

• Python
• Machine learning
• LLMs
• Verilog / RTL

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