DFT (Design For Test) Engineer

Summary

Full-time role at Etched, ASIC team. RoleRadar classifies it as software engineering. Listed location: San Jose. The posting asks for 10+ years of experience. Skills mentioned include Python and Verilog / RTL.

Generated by RoleRadar from facts in the posting. We don't reproduce the job description; read it in full on Etched's job page.

Key facts

Salary

$150K–$350K/yr

Published in the employer's job board data.

Location

• San Jose

Workplace

On-site

From the workplace field on the employer's job board.

Countries

United States

Inferred by RoleRadar from the listed locations.

Experience

10+ years asked for

PhD

Not mentioned

Visa sponsorship

Not stated in the posting

Team

ASIC

Skills mentioned

• Python
• Verilog / RTL

Links go to free learning resources, official documentation where it exists. No affiliate links.